1. Technical Field
The present invention relates to a submicron bipolar transistor structure with a buried silicide region and, more particularly, to a structure and method of fabricating the same which provides reduced extrinsic base resistance and a submicron emitter structure.
2. Description of the Prior Art
The direction of technology in the field of semiconductor devices is toward a device structure with high speed and low power consumption. This structure demands active regions which are shallow in depth and placed as close together as possible. In particular, it is required that the emitter region be made as shallow as possible and the width of the emitter-base junction be made as narrow as possible.
Many prior art structures and techniques exist which address these issues. U.S. Pat. No. 3,833,429 issued to Y. Monma et al on Sept. 3, 1974 describes a high speed bipolar transistor structure with a dual nitride film wherein the emitter diffusion will occur only in an overlapped portion between the two films. Thus, the emitter size may be substantially reduced. U.S. Pat. No. 4,151,009 issued to F. M. Ogureck et al on Apr. 24, 1979 discloses a high speed bipolar transistor structure with ion implanted compensating impurities formed in the base region near the base-collector junction to reduce the effective base width. An alternative structure is disclosed in U.S. Pat. No. 4,338,138 issued to J. R. Cavaliere et al on July 6, 1982. The Cavaliere et al structure exhibits reduced base-collector capacitance due to the very small area of the base-collector junction and a longated conductivity region surrounding the entire structure. A method of forming very shallow regions is disclosed in U.S. Pat. No. 4,494,010 issued to D. Kanzer on Jan. 22, 1985 wherein undoped polysilicon is first applied to the substrate and subsequently doped by ion implantation in selected regions to form the shallow contacts. A relatively new submicron bipolar structure has been proposes by T. Sakai et al in a paper entitled "Prospects of SST Technology for High Speed LSI", appearing in IEDM 85 at pp. 18-21. This structure, referred to as super self-aligned, includes submicron width base electrodes as well as submicron base and emitter contacts. Doped polysilicon is used as a diffusion source for the base and emitter regions to provide these submicron features. The resultant structure exhibits a considerably reduced collector-base capacitance.
One problem with these and other prior art arrangements is the value of the extrinsic base resistance associated with the final structure. At very high frequencies, this extrinsic base resistance often becomes the dominant impediment to improved performance. Therefore, it is necessary to reduce this resistance to as small a value as possible. One structure which exhibits reduced extrinsic base resistance is disclosed in U.S. Pat. No. 4,573,256 issued to J. S. Lechaton et al on Mar. 4, 1986. In this structure, a p+ region is formed in the extrinsic base region by ion implanting with a p type dopant to a depth less than the emitter region. The use of this high conductivity p+ region closely adjacent to the emitter thus reduces the extrinsic base resistance.
It is yet desirable to find alternative methods of reducing the extrinsic base resistance and submicron size active regions which require fewer masking and implanting procedures than associated with the structures described above.